This invention relates to a semiconductor memory device and method such as a RAM or an EPROM assembled in apparatus such as a telephone system, etc., and more particularly to a memory drive device and method including a control circuit for controlling an access to the memory, and having a function of resetting the state of the control circuit at the time when a power supply of the equipment is turned on, or at the time of recovery of interruption to service, etc. and a memory drive method using this device.
Generally, semiconductor memories become operative by delivering an address signal and various control signals from a memory control circuit such as a microcomputer to such memories. In apparatus, such as, for example, a telephone system including a semiconductor memory incorporated therein, at the time of turning a power on, or at the time of recovery of service interruption, it is necessary to deliver, to a memory control circuit, a reset command in order to initiate the operation in a normal state to return its internal status to a predetermined initial state.
In the case where semiconductor memories are of the type necessary to be supplied with a power at all times, such as a RAM or an EPROM, a backup power supply is required for ensuring supply of power at the time of service interruption of a main power supply. Since such a backup power supply is ordinarily a battery, it is dissipated when used for a long time. In the case where the main power supply service interruption is recovered after the backup power supply has been dissipated, information stored in a memory have been already deteriorated or vanished. Accordingly, it is necessary for initiating a normal operation to clear the information stored in the memory. This clear operation is practically carried out by delivering a memory clear command when a reset command is delivered to the memory control circuit.
As described in detail later, conventional memory drive devices include a RC time constant circuit connected to the main power supply line as a circuit for delivering a reset command to the memory control circuit. This RC time constant circuit generates a voltage signal gently rising in a ramp form depending upon a time constant when a main power supply voltage has rised in a step form at the time of turning a main power supply on, or at the time of recovery of interruption to service. This voltage signal is applied to the memory control circuit as a reset signal. When the memory control circuit has been operative by the step-shaped rising of the power supply voltage, the reset signal is in the state where its voltage level is lower than a predetermined threshold level, i.e., its logic level is low ("L"). The memory control circuit recognizes the "L" level of the reset signal as a reset command, thus to initialize the internal status.
However, in the case where the main power supply voltage gently rises in a time nearly to a time constant of the RC time constant circuit or more for any reason, since the reset signal is in the state where the voltage level is higher than a threshold level, i.e., the logic level is high ("H") when the memory control circuit has been in an operating state, there is the problem that the memory control circuit cannot be reset.
Further, such conventional memory drive circuits only include a manual switch for the purpose of delivering a memory clear command to the memory control circuit. Namely, whether memory should be cleared or not depends upon the judgment by user. However, there is great possibility that user forgets clearing the memory without being aware of dissipation of the backup power supply.
As stated above, the conventional memory drive devices cannot ensure that the operation of the apparatus is initiated in a normal state at the time when a main power supply is turned on, or at the time of recovery of interruption to service.